(1) Field of the Invention
The present invention relates to a 3-value input buffer circuit, and more particularly to a 3-value input buffer circuit adapted to an integrated circuit of a complementary MOS configuration.
(2) Description of the Related Art
Conventionally, a 3-value input buffer circuit of the kind to which the present invention relates is used in a circuit such as a complementary type MOS integrated circuit.
A conventional 3-value input buffer circuit is shown in FIG. 1. As shown therein, this 3-value input buffer circuit is constituted by a voltage dividing circuit which has resistors 14 and 15 connected to an input terminal 1 and two inverters whose circuit threshold voltages are different from each other. That is, the first one of the two inverters is constituted by a P-channel MOS transistor (hereinafter referred to as a "PMOS") 21 and an N-channel MOS transistor (hereinafter referred to as an "NMOS") 22, and is connected between an input terminal 1 and a first output terminal 2. Similarly, the second one of the two inverters is constituted by a PMOS 23 and an NMOS 24 and is connected between the input terminal 1 and a second output terminal 3. In this buffer circuit, the three levels of the common input terminal 1, namely, a high level, a low level and an open level, are detected, and the levels of the input terminal 1 are conveyed to internal circuits through the first output terminal 2 and the second output terminal 3.
The circuit threshold voltage of the complementary MOS type inverters explained above is given by the following equation (1): ##EQU1##
In the above equation (1), V.sub.Tp, K.sub.p, W.sub.p and L.sub.p represent respectively a threshold voltage, a mutual conductance, a gate width and a gate length of the PMOS. Similarly, V.sub.TN, K.sub.N, W.sub.N and L.sub.N represent respectively a threshold voltage, a mutual conductance, a gate width and a gate length of the NMOS.
In the foregoing 3-value input buffer circuit, if the circuit threshold voltage of the first inverter is to be set to 2.5V, the values concerned will be Wp=11.2 .mu.m, L.sub.p = 2 .mu.m, W.sub.N =5 .mu.m and L.sub.N =2 .mu.m. Likewise, if the circuit threshold voltage of the second inverter is to be set to 1.5V, the values concerned will be W.sub.p =5 .mu.m, L.sub.p =2 .mu.m, W.sub.N =8.5 .mu.m and L.sub.N =2 .mu.m. This, however, is on the assumption that V.sub.Tp =-0.8V, V.sub.TN =0.7V, K.sub.p =20.mu. and K.sub.N =40.mu..
FIG. 2 is a circuit diagram showing an example of another conventional 3-value input buffer circuit. As shown therein, this buffer circuit is equipped with a first inverter of a high circuit threshold voltage formed by PMOSs 25 and 26 and a second inverter of a low circuit threshold voltage formed by NMOSs 27 and 28. A voltage dividing circuit is constituted by resistors 14 and 15, and an intermediate point thereof is connected to a common input terminal 1 of the first inverter and the second inverter.
Similarly as in the example given above, the circuit threshold voltage of the first inverter constituted by the PMOSs 25 and 26 is given by the following equation (2): ##EQU2##
In the above equation (2), V.sub.TP1, K.sub.P1, W.sub.P1 and L.sub.P1 represent respectively a threshold voltage, a mutual conductance, a gate width and a gate length of the PMOS 25. Similarly, V.sub.TP2, K.sub.P2, W.sub.P2 and L.sub.P2 represent respectively a threshold voltage, a mutual conductance, a gate width and a gate length of the PMOS 26.
On the other hand, the circuit threshold voltage of the second inverter constituted by the NMOSs 27 and 28 is given by the following equation (3): ##EQU3##
In the above equation (3), V.sub.TN1, K.sub.N1, W.sub.N1 and L.sub.N1 represent respectively a threshold voltage, a mutual conductance, a gate width and a gate length of the NMOS 28, and V.sub.TN2, K.sub.N2, W.sub.N2 and L.sub.N2 represent respectively a threshold voltage, a mutual conductance, a gate width and a gate length of the NMOS 27.
In the foregoing 3-value input buffer circuit, if the circuit threshold voltage of the first inverter is to be set to 2.5V, the values concerned will be W.sub.P1 =7.3 .mu.m, L.sub.P1 =2 .mu.m, W.sub.P2 =5 .mu.m and L.sub.P2 =2 .mu.m. Likewise, if the circuit threshold voltage of the second inverter is to be set to 1.5V, the values concerned will be W.sub.N1 =34.5 .mu.m, L.sub.N1 =2 .mu.m, W.sub.N2 =5 .mu.m and L.sub.N2 =2 .mu.m. This, however, is on the assumption that V.sub.TP1 =-0.8V, V.sub.TP2 =-1.5V, V.sub.TN1 =0.7V, and V.sub.TN2 =1.4V. Here, large values of V.sub.TP2 and V.sub.TN2 are due to substrate biasing effects.
In the former example of the two conventional 3-value input buffer circuits explained above, there is a defect that, for obtaining a desired circuit threshold value, the areas of the respective transistors will become large, and there is also a defect that, since two complementary MOS type inverters are used, the circuit will likely be affected by variations in threshold voltages of the MOS transistors, thereby making it difficult to design the circuit.
In the latter example, the defects as compared with the former example have been reduced. However, since the inverter is constituted by the MOS transistors of the same polarity, there is a defect in that a through-current flows even when the input terminal is in an open state. That is, the through-current of about 100 .mu.A flows in the example explained above. Generally, in the case of the 3-value input buffer circuit, the input terminal often turns to an open state in its normal state, The flow of the through-current presents a problem in that current consumption cannot be effectively suppressed.